Chip stacks comprising a plurality of integrated semiconductor circuit dies arranged above each other are a way of increasing device densities of, for example, random access memory devices. Conventionally, such chip stacks may be implemented by adding additional redistribution layers to the individual semiconductor dies and wirebonding each individual semiconductor die. This may add additional capacitances and parasitics. Additionally, the redistribution layers and wirebond connections may require additional space at the edges of the individual semiconductor dies. Furthermore, integrated circuit dies designed for stand-alone use may not easily be utilized in a chip stack but may require major layout changes and a full-level re-design.